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ADP1829
SETTING THE CURRENT LIMIT
V IN
Data Sheet
The current-limit comparator measures the voltage across the
low-side MOSFET to determine the load current.
The current limit is set through the current-limit resistor, R CL .
The current sense pins, CSL1 and CSL2, source 50 μA through
their respective R CL . This creates an offset voltage of R CL multiplied
by the 50 μA CSL current. When the drop across the low-side
ADP1829
DH
DL
CSL
M1
M2
R LO
L
R HI
V OUT
C OUT
R CL =
I LPK R DSON ( MAX )
R LO =
I PKFOLDBACK R DSON ( MAX )
R HI =
V OUT
R DSON ( MAX )
R TOP = R BOT ? OUT
? V ? V FB ?
(18)
?
?
MOSFET R DSON is equal to or greater than this offset voltage, the
ADP1829 flags a current-limit event.
Because the CSL current and the MOSFET R DSON vary over
process and temperature, the minimum current limit should be
set to ensure that the system can handle the maximum desired
load current. To do this, use the peak current in the inductor,
which is the desired current-limit level plus the ripple current,
the maximum R DSON of the MOSFET at its highest expected
temperature, and the minimum CSL current.
(15)
44 μA
where I LPK is the peak inductor current.
In addition, the ADP1829 offers a technique for implementing
a current-limit foldback in the event of a short circuit with the
use of an additional resistor, as shown in Figure 25. Resistor R LO
is largely responsible for setting the foldback current limit during
a short circuit, and R HI is mainly responsible for setting up the
normal current limit. R LO is lower than R HI . These current-limit
sense resistors can be calculated by
(16)
44 μA
(17)
I LPK ? 44 μA
R LO
where:
I PKFOLDBACK is the desired short circuit peak inductor current limit.
I LPK is the peak inductor current limit during normal operation
and is also used in Equation 15.
Figure 25. Short Circuit Current Foldback Scheme
Because the buck converters are usually running fairly high
current, PCB layout and component placement may affect the
current-limit setting. An iteration of the R CL or R LO and R HI
values may be required for a particular board layout and
MOSFET selection. If alternate MOSFETs are substituted at
some point in production, these resistor values may also need
an iteration.
FEEDBACK VOLTAGE DIVIDER
The output regulation voltage is set through the feedback
voltage divider. The output voltage is reduced through the
voltage divider and drives the FB feedback input. The regulation
threshold at FB is 0.6 V. The maximum input bias current into
FB is 100 nA. For a 0.15% degradation in regulation voltage and
with 100 nA bias current, the low-side resistor, R BOT , needs to be
less than 9 k?, which results in 67 μA of divider current. For
R BOT , use 1 kΩ to 10 kΩ. A larger value resistor can be used, but
would result in a reduction in output voltage accuracy due to
the input bias current at the FB pin, while lower values cause
increased quiescent current consumption. Choose R TOP to set
the output voltage by using the following equation:
?
? V FB ?
where:
R TOP is the high-side voltage divider resistance.
R BOT is the low-side voltage divider resistance.
V OUT is the regulated output voltage.
V FB is the feedback regulation threshold, 0.6 V.
Rev. C | Page 18 of 28
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